This invention relates generally to an integrated circuit using an insulated gate field effect transistor and, more particularly, to an integrated circuit which effectively utilizes an electrical current conduction due to a punch-through phenomena in an insulated gate field effect transistor. This invention is useful for an integrated circuit in which a high speed operation is particularly required.
The enhancement type MOS field effect transistor, as the most general type of insulated gate field effect transistor, is suitable as a transistor to be used in an integrated circuit for an electronic computing circuit (logic circuit). However, attempts to improve the operational characteristics by shortening the channels of the MOS field effect transistor have been hindered by a so-called punch-through phenomena.
The punch-through current due to the punch-through phenomena has the characteristics that: this current flows not only on the surface but also in deep layers of semiconductor substrate, which causes an increase of the cross section of the electric current and an increase of the carrier mobility; the carrier transits in a high voltage electrical field, which causes a high saturation velocity of a carrier, and; the impurity atom concentration in the substrate can be rendered small which causes less stray capacitance of the device. These characteristics are suitable for high speed operation of a transistor.
In spite of the above-mentioned favourable characteristics, the practical utilization of the punch-through phenomena has been deemed to be difficult, because it has been considered that the nature of the punch-through current is not of the normally-off type, the control of the switching of the punch-through current by the gate is impossible, and the design of the device is not easy due to the need for linear representation of the two-dimentional phenomena of the punch-through current.